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| FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet FEATURES: * 8-bit 8051-Compatible Microcontroller (MCU) with Embedded SuperFlash Memory - Fully Software Compatible - Development Toolset Compatible - Pin-for-Pin Package Compatible * SST89E5xRC Operation - 0 to 33MHz at 5V * Total 512 Byte Internal RAM (256 Byte by default + 256 Byte enabled by software) * Single Block SuperFlash EEPROM - SST89E54RC: 16 KByte primary partition + 1 KByte secondary partition - SST89E52RC: 8 KByte primary partition + 1 KByte secondary partition - Primary Partition is divided into Four Pages - Secondary Partition has One Page - Individual Page Security Lock - In-System Programming (ISP) - In-Application Programming (IAP) - Small-Sector Architecture: 128-Byte Sector Size * Support External Address Range up to 64 KByte of Program and Data Memory * Three High-Current Port 1 pins (16 mA each) * Three 16-bit Timers/Counters * Full-Duplex, Enhanced UART - Framing error detection - Automatic address recognition * Eight Interrupt Sources at 4 Priority Levels * Programmable Watchdog Timer (WDT) * Four 8-bit I/O Ports (32 I/O Pins) * Second DPTR register * Low EMI Mode (Inhibit ALE) * Standard 12 Clocks per cycle, the device has an option to double the speed to 6 clocks per cycle. * TTL- and CMOS-Compatible Logic Levels * Low Power Modes - Power-down Mode with External Interrupt Wake-up - Idle Mode * Selectable Operation Clock - Divide down to 1/4, 1/16, 1/256, or 1/1024th * Temperature Ranges: - Commercial (0C to +70C) * Packages Available - 40-pin PDIP - 44-lead PLCC * All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION The SST89E52RC / SST89E54RC are members of the FlashFlex family of 8-bit microcontroller products designed and manufactured with SST's patented and proprietary SuperFlash CMOS semiconductor process technology. The split-gate cell design and thick-oxide tunneling injector offer significant cost and reliability benefits for our customers.The devices use the 8051 instruction set and are pinfor-pin compatible with standard 8051 microcontroller devices. The device comes with 17/9 KByte of on-chip flash EEPROM program memory which is divided into 2 independent program memory partitions. The primary partition occupies 16/8 KByte of internal program memory space and the secondary partition occupies 1 KByte of internal program memory space. The flash memory can be programmed via a standard 87C5x OTP EPROM programmer fitted with a special adapter and firmware for SST's devices. During power-on reset, the devices can be configured as either a slave to an external host for source code storage or a master to an (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 1 external host for an in-system programming (ISP) operation. The devices are designed to be programmed in-system on the printed circuit board for maximum flexibility. An example of the bootstrap loader (BSL) in memory, demonstrating initial user program code loading or subsequent user code updating via an ISP operation, is provided on the SST website. The sample BSL is for the user's reference only; SST does not guarantee its functionality. In addition to 17/9 KByte of SuperFlash EEPROM program memory on-chip and 512 x8 bits of on-chip RAM, the device can address up to 64 KByte of external program memory and up to 64 KByte of external RAM. The highly-reliable, patented SST SuperFlash technology and memory cell architecture have a number of important advantages for designing and manufacturing flash EEPROMs. These advantages translate into significant cost and reliability benefits for our customers. The SST logo, SuperFlash, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet TABLE OF CONTENTS FEATURES: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 LIST OF TABLES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.0 FUNCTIONAL BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.0 PIN ASSIGNMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.0 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 Program Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 Data RAM Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 Expanded Data RAM Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4 Dual Data Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.5 Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.0 FLASH MEMORY PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.1 Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2 In-Application Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.3 In-System Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.0 TIMERS/COUNTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2 Timer Set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.3 Programmable Clock-Out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.0 SERIAL I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1 Full-Duplex, Enhanced UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.0 WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1 Watchdog Timer Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2 Pure Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.3 Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.4 Feed Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.5 Power Saving Considerations for Using the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.0 SECURITY LOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.1 Chip-Level Security Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.2 Page-Level Security Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.3 Read Operation Under Lock Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.0 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.2 Boot Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.3 Interrupt Priority and Polling Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.0 POWER-SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.1 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.2 Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 2 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet 11.0 SYSTEM CLOCK AND CLOCK OPTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11.1 Clock Input Options and Recommended Capacitor Values for Oscillator . . . . . . . . . . . . . . . . . . . . . . 44 11.2 Clock Doubling Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11.3 Clock Divider Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12.0 ELECTRICAL SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.1 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 12.2 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 13.0 PRODUCT ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 13.1 Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 14.0 PACKAGING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 LIST OF FIGURES FIGURE 1: Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 FIGURE 2-1: Pin Assignments for 40-pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 FIGURE 2-2: Pin Assignments for 44-lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 FIGURE 3-1: Internal and External Data Memory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 FIGURE 3-2: Program Memory Organization and Code Security Protection. . . . . . . . . . . . . . . . . . . . . . . . 11 FIGURE 3-3: Dual Data Pointer Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 FIGURE 6-1: Framing Error Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 FIGURE 6-2: UART Timings in Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 FIGURE 6-3: UART Timings in Modes 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 FIGURE 7-1: Block Diagram of Programmable Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 FIGURE 9-1: Power-on Reset Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 FIGURE 9-2: Boot Sequence Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 FIGURE 9-3: Hardware Pin Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 FIGURE 9-4: Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 FIGURE 11-1: Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 FIGURE 12-1: External Program Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 FIGURE 12-2: External Data Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 FIGURE 12-3: External Data Memory Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 FIGURE 12-4: External Clock Drive Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 FIGURE 12-5: Shift Register Mode Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 FIGURE 12-6: AC Testing Input/Output Test Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 FIGURE 12-7: Float Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 FIGURE 12-8: A Test Load Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 FIGURE 12-9: IDD Test Condition, Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 FIGURE 12-10: IDD Test Condition, Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 FIGURE 12-11: IDD Test Condition, Power-down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 FIGURE 14-1: 40-pin Plastic Dual In-line Pins (PDIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 FIGURE 14-2: 44-lead Plastic Lead Chip Carrier (PLCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 3 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet LIST OF TABLES TABLE 2-1: Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 TABLE 3-1: External Data Memory RD#, WR# with EXTRAM bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 TABLE 3-2: FlashFlex SFR Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 TABLE 3-3: CPU related SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 TABLE 3-4: Flash Memory Programming SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 TABLE 3-5: Watchdog Timer SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 TABLE 3-6: Feed Sequence SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 TABLE 3-7: Timer/Counters SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 TABLE 3-8: Interface SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 TABLE 3-9: Clock Option SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 TABLE 4-1: Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 TABLE 4-2: Default Boot Vector Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 TABLE 4-3: IAP COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 TABLE 5-1: Timer/Counter 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 TABLE 5-2: Timer/Counter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 TABLE 5-3: Timer/Counter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 TABLE 9-1: Boot Vector Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 TABLE 9-2: Interrupt Polling Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 TABLE 10-1: Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 TABLE 11-1: Recommended Values for C1 and C2 by Crystal Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 TABLE 11-2: Clock Doubling Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 TABLE 12-1: Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 TABLE 12-2: Reliability Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 TABLE 12-3: AC Conditions of Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 TABLE 12-4: Recommended System Power-up Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 TABLE 12-5: Pin Impedance (TA=25 C, f=1 Mhz, other pins open) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 TABLE 12-6: DC Characteristics for SST89E5xRC: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 TABLE 12-7: AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 TABLE 12-8: External Clock Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 TABLE 12-9: Serial Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 TABLE 12-10: Flash Memory Programming/Verification Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 TABLE 14-1: Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 4 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet 1.0 FUNCTIONAL BLOCKS 8051 CPU Core ALU, ACC, B-Register, Instruction Register, Program Counter, Timing and Control Oscillator Interrupt Control 8 Interrupts Watchdog Timer Flash Control Unit SuperFlash EEPROM Primary Partition 16K x8 for SST89x54RC 8K x8 for SST89x52RC RAM 512 x8 8 I/O Port 0 8 I/O I/O 8 I/O Port 2 I/O 8 I/O Port 3 I/O Secondary Partition 1K x8 Timer 0 (16-bit) Security Lock I/O Port 1 Timer 1 (16-bit) 8-bit Enhanced UART 1259 B1.3 Timer 2 (16-bit) FIGURE 1: Functional Block Diagram (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 5 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet 2.0 PIN ASSIGNMENTS (T2) P1.0 (T2 EX) P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD) P3.0 (TXD) P3.1 (INT0#) P3.2 (INT1#) P3.3 (T0) P3.4 (T1) P3.5 (WR#) P3.6 (RD#) P3.7 XTAL2 XTAL1 VSS 1 2 3 4 5 6 7 8 40 39 38 37 36 35 34 VDD P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA# ALE/PROG# PSEN# P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11) P2.2 (A10) P2.1 (A9) P2.0 (A8) 1259 40-pdip PI P1.1 40-pin PDIP Top View 33 32 9 31 10 11 12 13 14 15 16 17 18 19 20 30 29 28 27 26 25 24 23 22 21 FIGURE 2-1: Pin Assignments for 40-pin PDIP P1.1 (T2 EX) P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) 6 P1.5 P1.6 P1.7 RST (RXD) P3.0 NC (TXD) P3.1 (INT0#) P3.2 (INT1#) P3.3 (T0) P3.4 (T1) P3.5 7 8 9 10 11 12 13 14 15 16 5 4 3 2 1 44 43 42 41 40 39 38 37 36 P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA# NC ALE/PROG# PSEN# P2.7 (A15) P2.6 (A14) P2.5 (A13) 44-lead PLCC Top View 17 29 18 19 20 21 22 23 24 25 26 27 28 (WR#) P3.6 (RD#) P3.7 XTAL2 XTAL1 NC (A8) P2.0 (A9) P2.1 (A10) P2.2 (A11) P2.3 (A12) P2.4 1259 44-plcc NJ P3.1 FIGURE 2-2: Pin Assignments for 44-lead PLCC S71259-04-000 1/07 (c)2007 Silicon Storage Technology, Inc. VSS 6 P0.3 (AD3) 35 34 33 32 31 30 P1.0 (T2) P1.4 P1.3 P1.2 VDD NC FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet 2.1 Pin Descriptions TABLE Symbol P0[7:0] 2-1: Pin Descriptions (1 of 2) Type1 I/O Name and Functions Port 0: Port 0 is an 8-bit open drain bi-directional I/O port. As an output port each pin can sink several LS TTL inputs. Port 0 pins that have `1's written to them float, and in this state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external code and data memory. In this application, it uses strong internal pull-ups when transitioning to `1's. Port 0 also receives the code bytes during the external host mode programming, and outputs the code bytes during the external host mode verification. External pull-ups are required during program verification or as a general purpose I/O port. P1[7:0] I/O with internal Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers pull-up can drive LS TTL inputs. Port 1 pins are pulled high by the internal pull-ups when `1's are written to them and can be used as inputs in this state. As inputs, Port 1 pins that are externally pulled low will source current (IIL, see Table 12-6) because of the internal pull-ups. P1[5, 6, 7] have high current drive of 16 mA. Port 1 also receives the low-order address byte during the external host mode programming and verification. I/O I I/O I/O I/O I/O I/O I/O I/O with internal pull-up T2: External count input to Timer/Counter 2 or Clock-out from Timer/Counter 2 T2EX: Timer/Counter 2 capture/reload trigger and direction control GPIO GPIO GPIO GPIO GPIO GPIO Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins are pulled high by the internal pull-ups when `1's are written to them and can be used as inputs in this state. As inputs, Port 2 pins that are externally pulled low will source current (IIL, see Table 12-6) because of the internal pull-ups. Port 2 sends the high-order address byte during fetches from external program memory and during accesses to external Data Memory that use 16-bit address (MOVX@DPTR). In this application, it uses strong internal pull-ups when transitioning to `1's. Port 2 also receives the high-order address byte during the external host mode programming and verification. Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can drive LS TTL inputs. Port 3 pins are pulled high by the internal pull-ups when `1's are written to them and can be used as inputs in this state. As inputs, Port 3 pins that are externally pulled low will source current (IIL, see Table 12-6) because of the internal pull-ups. Port 3 also receives the high-order address byte during the external host mode programming and verification. RXD: Universal Asynchronous Receiver/Transmitter (UART) - Receive input TXD: UART - Transmit output INT0#: External Interrupt 0 Input INT1#: External Interrupt 1 Input T0: External count input to Timer/Counter 0 T1: External count input to Timer/Counter 1 WR#: External Data Memory Write strobe RD#: External Data Memory Read strobe P1[0] P1[1] P1[2] P1[3] P1[4] P1[5] P1[6] P1[7] P2[7:0] P3[7:0] I/O with internal pull-up P3[0] P3[1] P3[2] P3[3] P3[4] P3[5] P3[6] P3[7] I O I I I I O O (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 7 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet TABLE Symbol PSEN# 2-1: Pin Descriptions (Continued) (2 of 2) Type1 I/O Name and Functions Program Store Enable: PSEN# is the Read strobe to external program. When the device is executing from internal program memory, PSEN# is inactive (High). When the device is executing code from external program memory, PSEN# is activated twice each machine cycle, except that two PSEN# activations are skipped during each access to external data memory. A forced high-to-low input transition on the PSEN# pin while the RST input is continually held high for more than 10 machine cycles will cause the device to enter external host mode programming. Reset: While the oscillator is running, a "high" logic state on this pin for two machine cycles will reset the device. If the PSEN# pin is driven by a high-to-low input transition while the RST input pin is held "high," the device will enter the external host mode, otherwise the device will enter the normal operation mode. External Access Enable: EA# must be connected to VSS in order to enable the device to fetch code from the external program memory. EA# must be strapped to VDD for internal program execution. However, Disable-Extern-Boot (See Section 8.0, "Security Lock") will disable EA#, and program execution is only possible from internal program memory. The EA# pin can tolerate a high voltage2 of 12V. (See Section 12.0, "Electrical Specification") Address Latch Enable: ALE is the output signal for latching the low byte of the address during an access to external memory. This pin is also the programming pulse input (PROG#) for flash programming. Normally the ALE3 is emitted at a constant rate of 1/6 the crystal frequency4 and can be used for external timing and clocking. One ALE pulse is skipped during each access to external data memory. However, if AO is set to 1, ALE is disabled. (See "Auxiliary Register (AUXR)" in Section 3.5, "Special Function Registers") No Connect Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier. Power Supply Ground T2-1.0 1259 RST I EA# I ALE/PROG# I/O NC XTAL1 XTAL2 VDD VSS I/O I O I I 1. I = Input; O = Output 2. It is not necessary to receive a 12V programming supply voltage during flash programming. 3.ALE loading issue: When ALE pin experiences higher loading (>30pf) during the reset, the MCU may accidentally enter into modes other than normal working mode. The solution is to add a pull-up resistor of 3-50 K to VDD, e.g. for ALE pin. 4. For 6 clock mode, ALE is emitted at 1/3 of crystal frequency. (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 8 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet 3.0 MEMORY ORGANIZATION The device has separate address spaces for program and data memory. When instructions access addresses in the upper 128 bytes (above 7FH), the MCU determines whether to access the SFRs or RAM by the type of instruction given. If it is indirect, then RAM is accessed. If it is direct, then an SFR is accessed. See the examples below. Indirect Access: MOV @R0, #data ; R0 contains 90H 3.1 Program Flash Memory There are two internal flash memory partitions in the device. The primary flash memory partition (Partition 0) has 16/8 KByte. The secondary flash memory partition (Partition 1) has 1 KByte. The total flash memory space of both partitions can be used as a contiguous code storage. The 16K/8K x8 primary flash partition is organized as 128/ 64 sectors, each sector consists of 128 Bytes. The primary partition is divided into four logical pages as shown in Figure 3-2 The 1K x8 secondary flash partition is organized as 8 sectors, each sector consists also of 128 Bytes. For both partitions, the 7 least significant program address bits select the byte within the sector. The remainder of the program address bits select the sector within the partition. Register R0 points to 90H which is located in the upper address range. Data in "#data" is written to RAM location 90H rather than port 1. Direct Access: MOV 90H, #data ; write data to P1 Data in "#data" is written to port 1. Instructions that write directly to the address write to the SFRs. To access the expanded RAM, the EXTRAM bit must be cleared and MOVX instructions must be used. The extra 256 Bytes of memory is physically located on the chip and logically occupies the first 256 bytes of external memory (addresses 000H to FFH). When EXTRAM = 0, the expanded RAM is indirectly addressed using the MOVX instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. Accessing the expanded RAM does not affect ports P0, P3.6 (WR#), P3.7 (RD#), or P2. With EXTRAM = 0, the expanded RAM can be accessed as in the following example. Expanded RAM Access (Indirect Addressing only): MOVX @DPTR, A ; DPTR contains 0A0H 3.2 Data RAM Memory The data RAM has 512 Bytes of internal memory. The first 256 Bytes are available by default. The second 256 Bytes are enabled by clearing the EXTRAM bit in the AUXR register. The RAM can be addressed up to 64 KByte for external data memory. 3.3 Expanded Data RAM Addressing The SST89E5xRC have the capability of 512 Bytes of RAM. See Figure 3-1. The device has four sections of internal data memory: 1. The lower 128 Bytes of RAM (00H to 7FH) are directly and indirectly addressable. 2. The higher 128 Bytes of RAM (80H to FFH) are indirectly addressable. 3. The special function registers (80H to FFH) are directly addressable only. 4. The expanded RAM of 256 Bytes (00H to FFH) is indirectly addressable by the move external instruction (MOVX) and clearing the EXTRAM bit. (See "Auxiliary Register (AUXR)" in Section 3.5, "Special Function Registers") Since the upper 128 bytes occupy the same addresses as the SFRs, the RAM must be accessed indirectly. The RAM and SFRs space are physically separate even though they have the same addresses. (c)2007 Silicon Storage Technology, Inc. DPTR points to 0A0H and data in "A" is written to address 0A0H of the expanded RAM rather than external memory. Access to external memory higher than FFH using the MOVX instruction will access external memory (0100H to FFFFH) and will perform in the same way as the standard 8051, with P0 and P2 as data/address bus, and P3.6 and P3.7 as write and read timing signals. When EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 8051. Using MOVX @Ri provides an 8-bit address with multiplexed data on Port 0. Other output port pins can be used to output higher order address bits. This provides external paging capabilities. Using MOVX @DPTR generates a 16-bit address. This allows external addressing up the 64K. Port 2 provides the high-order eight address bits (DPH), and Port 0 multiplexes the low order eight address bits (DPL) with data. Both MOVX @Ri and MOVX @DPTR generates the necessary S71259-04-000 1/07 9 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet read and write signals (P3.6 - WR# and P3.7 - RD#) for external memory use. Table 3-1 shows external data memory RD#, WR# operation with EXTRAM bit. The stack pointer (SP) can be located anywhere within the 256 bytes of internal RAM (lower 128 bytes and upper 128 bytes). The stack pointer may not be located in any part of the expanded RAM. TABLE 3-1: External Data Memory RD#, WR# with EXTRAM bit MOVX @DPTR, A or MOVX A, @DPTR MOVX @Ri, A or MOVX A, @Ri ADDR = Any RD# / WR# not asserted1 RD# / WR# asserted T3-1.0 1259 AUXR EXTRAM = 0 EXTRAM = 1 ADDR < 0100H RD# / WR# not asserted RD# / WR# asserted ADDR >= 0100H RD# / WR# asserted RD# / WR# asserted 1. Access limited to ERAM address within 0 to 0FFH. FFH FFH (Indirect Addressing) FFH (Direct Addressing) Special Function Registers (SFRs) Expanded RAM 256 Bytes 80H 7FH Upper 128 Bytes Internal RAM Lower 128 Bytes Internal RAM 80H (Indirect Addressing) 000H 00H (Indirect & Direct Addressing) FFFFH (Indirect Addressing) FFFFH (Indirect Addressing) External Data Memory External Data Memory 0100H FFH Expanded RAM 000H EXTRAM = 0 0000H EXTRAM = 1 1259 F01.0 FIGURE 3-1: Internal and External Data Memory Structure S71259-04-000 1/07 (c)2007 Silicon Storage Technology, Inc. 10 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet EA# = 0 FFFFH EA# = 1 Secondary Partition 3FFFH 1KByte Page 4KByte Page Primary Partition External 64 KByte 4KByte Page Secondary Partition 1FFFH EA# = 1 1KByte Page 2KByte Page Primary Partition 0000H 4KByte Page 2KByte Page 2KByte Page 4KByte Page 0000H 0000H 2KByte Page SST89E54RC SST89E52RC 1259 F02.3 FIGURE 3-2: Program Memory Organization and Code Security Protection 3.4 Dual Data Pointers The device has two 16-bit data pointers. The DPTR Select (DPS) bit in AUXR1 determines which of the two data pointers is accessed. When DPS=0, DPTR0 is selected; when DPS=1, DPTR1 is selected. Quickly switching between the two data pointers can be accomplished by a single INC instruction on AUXR1. (See Figure 3-3) 3.5 Special Function Registers Most of the unique features of the FlashFlex microcontroller family are controlled by bits in special function registers (SFRs) located in the SFR memory map shown in Table 32. Individual descriptions of each SFR are provided and reset values indicated in Tables 3-3 to 3-8. AUXR1 / bit0 DPS DPTR1 DPTR0 DPH 83H DPL 82H 1259 F03.0 DPS = 0 DPTR0 DPS = 1 DPTR1 External Data Memory FIGURE 3-3: Dual Data Pointer Organization S71259-04-000 1/07 (c)2007 Silicon Storage Technology, Inc. 11 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet TABLE F8H F0H E8H E0H D8H D0H C8H C0H B8H B0H A8H A0H 98H 90H 88H 80H PSW1 T2CON1 WDTC1 IP1 P31 IE1 P21 SCON1 P11 TCON1 P01 TMOD SP TL0 DPL TL1 DPH TH0 TH1 WDTD AUXR PCON SADEN SFCF SADDR PMC SBUF SFIS0 AUXR1 SFCM SFAL SFAH SFDT SFST T2MOD RCAP2L RCAP2H TL2 SFIS1 COSR IPH SPCR TH2 3-2: FlashFlex SFR Memory Map 8 BYTES IPA1 B1 IEA1 ACC1 IPAH FFH F7H EFH E7H DFH D7H CFH C7H BFH B7H AFH A7H 9FH 97H 8FH 87H T3-2.1 1259 1. Bit addressable SFRs (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 12 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet TABLE 3-3: CPU related SFRs Direct Address E0H F0H D0H 81H 82H 83H A8H E8H B8H B7H F8H F7H 87H 8EH A2H A1H EA EC EWD PPCH PWD PWDH ET2 PT2 CY AC F0 Bit Address, Symbol, or Alternative Port Function MSB ACC[7:0] B[7:0] RS1 RS0 OV F1 P LSB Reset Value 00H 00H 00H 07H 00H 00H EX1 PX1 PX1H GF0 0 ET0 PT0 PT0H PD EXTRAM EX0 PX0 PX0H IDL AO DPS 00H x0xxxxxxb x0000000b x0000000b x0xxxxxxb x0xxxxxxb 00x10000b xxxxxxx00b xxxx00x0b xx000000b Symbol Description ACC1 B1 PSW1 SP DPL DPH IE1 IEA1 IP1 IPH IPA1 IPAH PCON AUXR AUXR1 PMC Accumulator B Register Program Status Word Stack Pointer Data Pointer Low Data Pointer High Interrupt Enable Interrupt Enable A Interrupt Priority Reg Interrupt Priority Reg High Interrupt Priority Reg A Interrupt Priority Reg A High Power Control Auxiliary Reg Auxiliary Reg 1 Power Management Control Register SP[7:0] DPL[7:0] DPH[7:0] ES PS ET1 PT1 PT1H GF1 GF2 PT2H PSH WDU POF TCT SMOD1 SMOD0 - TCT2 PB2 PB1 UART T3-3.1 1259 1. Bit Addressable SFRs (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 13 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet TABLE 3-4: Flash Memory Programming SFRs Direct Address B1H B2H B3H Bit Address, Symbol, or Alternative Port Function MSB CMD_ Status IAPEN HWIAP FCM[6:0] SuperFlash Low Order Byte Address Register A7 to A0 (SFAL) SuperFlash High Order Byte Address Register A15 to A8 (SFAH) SuperFlash Data Register Manufacturer's ID SFST_SEL Symbol Description SFCF SFCM SFAL SuperFlash Configuration SuperFlash Command SuperFlash Address Low SuperFlash Address High SuperFlash Data LSB Reset Value 10000000b 00H 00H SFAH B4H 00H SFDT B5H B6H SFST_SEL= 0H SFST_SEL= 1H SFST_SEL= 2H SFST_SEL= 3H SFST_SEL= 4H SFST_SEL= 5H X Boot From Zero BootFromUserVector 00H BFH Device ID0 (F7H indicates Device ID1 is real ID) Device ID1 Boot Vector PAGE4 Enable ClockDouble PAGE3 DisableExternHostCmd PAGE2 DisableExternMOVC PAGE1 DisableExternBoot PAGE0 DisableExternIAP T3-4.0 1259 SFST SuperFlash Status TABLE 3-5: Watchdog Timer SFRs Direct Address C0H 85H Bit Address, Symbol, or Alternative Port Function MSB WDTON WDFE WDRE WDTS WDT LSB SWDT Reset Value x0000000b 00H T3-5.0 1259 Symbol Description WDTC1 Watchdog Timer Control WDTD Watchdog Timer Data/Reload Watchdog Timer Data/Reload 1. Bit Addressable SFRs TABLE 3-6: Feed Sequence SFRs Direct Address 97H C4H Bit Address, Symbol, or Alternative Port Function MSB (Write only) (Write only) LSB Reset Value 00H 00H T3-6.0 1259 Symbol Description SFIS0 SFIS1 Sequence Reg 0 Sequence Reg 1 (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 14 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet TABLE Symbol TMOD TCON1 TH0 TL0 TH1 TL1 3-7: Timer/Counters SFRs Description Timer/Counter Mode Control Timer/Counter Control Timer 0 MSB Timer 0 LSB Timer 1 MSB Timer 1 LSB Direct Address 89H GATE 88H 8CH 8AH 8DH 8BH C8H C9H CDH CCH CBH CAH TF2 EXF2 RCLK TF1 Bit Address, Symbol, or Alternative Port Function MSB Timer 1 C/T# TR1 M1 TF0 M0 TR0 GATE IE1 TH0[7:0] TL0[7:0] TH1[7:0] TL1[7:0] TCLK EXEN2 TH2[7:0] TL2[7:0] RCAP2H[7:0] RCAP2L[7:0] TR2 C/T2# T2OE CP/RL2# DCEN Timer 0 C/T# IT1 M1 IE0 M0 IT0 00H 00H 00H 00H 00H 00H xxxxxx00b 00H 00H 00H 00H T3-7.0 1259 LSB Reset Value 00H T2CON1 Timer / Counter 2 Control T2MOD# Timer2 Mode Control TH2 TL2 Timer 2 MSB Timer 2 LSB RCAP2H Timer 2 Capture MSB RCAP2L Timer 2 Capture LSB 1. Bit Addressable SFRs TABLE 3-8: Interface SFRs Direct Address 99H 98H A9H B9H 80H 90H A0H B0H RD# WR# T1 SM0/FE SM1 SM2 Bit Address, Symbol, or Alternative Port Function MSB SBUF[7:0] REN TB8 RB8 TI RI SADDR[7:0] SADEN[7:0] P0[7:0] P2[7:0] T0 INT1# INT0# TXD RXD T2EX T2 LSB RESET Value Indeterminate 00H 00H 00H FFH FFH FFH FFH T3-8.1 1259 Symbol Description SBUF SCON1 Serial Data Buffer Serial Port Control SADDR Slave Address SADEN Slave Address Mask P01 P11 P21 P31 Port 0 Port 1 Port 2 Port 3 1. Bit Addressable SFRs TABLE Symbol COSR 3-9: Clock Option SFR Description Clock Option Register Direct Address BFH Bit Address, Symbol, or Alternative Port Function MSB COEN CO_REL LSB CO_IN Reset Value 0x00000b (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 15 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet SuperFlash Configuration Register (SFCF) Location B1H 7 CMD_ Status 6 IAPEN 5 4 HWIAP 3 2 1 SFST_SEL 0 Reset Value 10000000b Symbol CMD_Status Function IAP Command Completion Status 0: IAP command is ignored 1: IAP command is completed fully IAP Enable Bit 0: Disable all IAP commands (Commands will be ignored) 1: Enable all IAP commands Boot Status Flag 0: System boots up without special pin configuration setup 1:System boots up with both P1[0] and P1[1] pins in logic low state curing reset. (See Figure 9-3.) Provide index to read back information when read to SFST register is executed. (See , "SuperFlash Status Register (SFST) (Read Only Register)" on page 18 for detailed settings.) IAPEN HWIAP SFST_SEL (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 16 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet SuperFlash Command Register (SFCM) Location B2H 7 6 FCM6 5 FCM5 4 FCM4 3 FCM3 2 FCM2 1 FCM1 0 FCM0 Reset Value 00H Symbol FCM[6:0] Function Reserved Flash operation command 000_0001b 000_1011b 000_1101b 000_1100b 000_1110b 000_0011b Chip-Erase Sector-Erase Partition0-Erase Byte-Verify1 Byte-Program Secure-Page Page-Level Security Commands SFAH=90H; Secure-Page0 SFAH=91H; Secure-Page1 SFAH=92H; Secure-Page2 SFAH=93H; Secure-Page3 SFAH=94H; Secure-Page4 000-0101b Secure-Chip Chip-Level Security Commands SFAH=B0H; Disable-Extern-IAP SFAH=B1H; Disable-Extern-Boot SFAH=B2H; Disable-Extern-MOVC SFAH=B3H; Disable-Extern-Host-Cmd 000-1000b Boot Options Boot Option Setting Commands SFAH=E0H; Enable-Clock-Double SFAH=E1H; Boot-From-User-Vector SFAH=E2H; Boot-From-Zero 000-1001b Set-User-Boot-Vector All other combinations are not implemented, and reserved for future use. 1. Byte-Verify has a single machine cycle latency and will not generate any INT1# interrupt regardless of FIE. SuperFlash Address Registers (SFAL) Location B3H 7 6 5 4 3 2 1 0 Reset Value 00H SuperFlash Low Order Byte Address Register Symbol SFAL Function Mailbox register for interfacing with flash memory block. (Low order address register). SuperFlash Address Registers (SFAH) Location B4H 7 6 5 4 3 2 1 0 Reset Value 00H SuperFlash High Order Byte Address Register Symbol SFAH Function Mailbox register for interfacing with flash memory block. (High order address register). (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 17 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet SuperFlash Data Register (SFDT) Location B5H 7 6 5 4 3 2 1 0 Reset Value 00H SuperFlash Data Register Symbol SFDT Function Mailbox register for interfacing with flash memory block. (Data register). SuperFlash Status Register (SFST) (Read Only Register) Location B6H 7 6 5 4 3 2 1 0 Reset Value 10111111b SuperFlash Status Register Symbol SFST Function This is a read-only register. The read-back value is indexed by SFST_SEL in the SuperFlash Configuration Register (SFCF). SFST_SEL=0H: Manufacturer's ID 1H: Device ID0 = F7H 2H: Device ID1 = Device ID (Refer to Table 4-1 on page 27) 3H: Boot Vector 4H: Page-Security bit setting 5H: Chip-Level Security bit setting and Boot Options (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 18 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet Interrupt Enable (IE) Location A8H 7 EA 6 5 ET2 4 ES 3 ET1 2 EX1 1 ET0 0 EX0 Reset Value 00H Symbol EA Function Global Interrupt Enable. 0 = Disable 1 = Enable Timer 2 Interrupt Enable. Serial Interrupt Enable. Timer 1 Interrupt Enable. External 1 Interrupt Enable. Timer 0 Interrupt Enable. External 0 Interrupt Enable. ET2 ES ET1 EX1 ET0 EX0 Interrupt Enable A (IEA) Location E8H 7 - 6 EWD 5 - 4 - 3 - 2 - 1 - 0 - Reset Value x0xxxxxxb Symbol EWD Function Watchdog Interrupt Enable. 1 = Enable the interrupt 0 = Disable the interrupt (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 19 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet Interrupt Priority (IP) Location B8H 7 6 5 PT2 4 PS 3 PT1 2 PX1 1 PT0 0 PX0 Reset Value x0000000b Symbol PT2 PS PT1 PX1 PT0 PX0 Function Timer 2 interrupt priority bit. Serial Port interrupt priority bit. Timer 1 interrupt priority bit. External interrupt 1 priority bit. Timer 0 interrupt priority bit. External interrupt 0 priority bit. Interrupt Priority High (IPH) Location B7H 7 6 5 PT2H 4 PSH 3 PT1H 2 PX1H 1 PT0H 0 PX0H Reset Value x0000000b Symbol PT2H PSH PT1H PX1H PT0H PX0H Interrupt Priority A (IPA) Location F8H 7 - Function Timer 2 interrupt priority bit high. Serial Port interrupt priority bit high. Timer 1 interrupt priority bit high. External interrupt 1 priority bit high. Timer 0 interrupt priority bit high. External interrupt 0 priority bit high. 6 PWD 5 - 4 - 3 - 2 - 1 - 0 - Reset Value x0xxxxxxb Symbol PWD Function Watchdog interrupt priority bit. Interrupt Priority A High (IPAH) Location F7H 7 6 PWDH 5 4 3 2 1 0 Reset Value x0xxxxxxb Symbol PWDH Function Watchdog interrupt priority bit high. (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 20 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet Auxiliary Register (AUXR) Location 8EH 7 6 5 4 3 2 1 EXTRAM 0 AO Reset Value xxxxxx10b Symbol EXTRAM Function Internal/External RAM access 0: Internal Expanded RAM access within range of 00H to FFH using MOVX @Ri / @DPTR. Beyond 100H, the MCU always accesses external data memory. For details, refer to Section 3.3, "Expanded Data RAM Addressing" . 1: External data memory access. Disable/Enable ALE 0: ALE is emitted at a constant rate of 1/3 the oscillator frequency in 6 clock mode, 1/6 fOSC in 12 clock mode. 1: ALE is active only during a MOVX or MOVC instruction. AO Auxiliary Register 1 (AUXR1) Location A2H 7 6 5 4 3 GF2 2 0 1 0 DPS Reset Value xxxx00x0b Symbol GF2 DPS Function General purpose user-defined flag DPTR registers select bit 0: DPTR0 is selected. 1: DPTR1 is selected. Sequence Register 0 (SFIS0) Location 97H 7 6 5 4 3 2 1 0 Reset Value N/A (Write only) Symbol SFIS0 Function Register used with SFIS1 to provide a feed sequence to validate writing to WDTC and SFCM. Without a proper feed sequence, writing to SFCM will be ignored and writing to WDTC in Watchdog mode will cause an immediate Watchdog reset. Sequence Register 1 (SFIS1) Location C4H 7 6 5 4 3 2 1 0 Reset Value N/A (Write only) Symbol SFIS1 Function Register used with SFIS0 to provide a feed sequence to validate writing to WDTC and SFCM. (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 21 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet Watchdog Timer Control Register (WDTC) Location C0H 7 6 WDTON 5 WDFE 4 3 WDRE 2 WDTS 1 WDT 0 SWDT Reset Value x0000000b Symbol WDTON Function Watchdog timer start control bit (Used in Watchdog mode) 0: Watchdog timer can be started or stopped freely during Watchdog mode. 1: Start Watchdog timer; bit cannot be cleared by software. Watchdog feed sequence error flag 0: Watchdog feed sequence error has not occurred. 1: Due to an incorrect feed sequence before writing to WDTC in Watchdog mode, the hardware entered Watchdog reset and set this flag to "1." This is for software to detect whether the Watchdog reset was caused by timer expiration or an incorrect feed sequence. Watchdog timer reset enable. 0: Disable Watchdog timer reset. 1: Enable Watchdog timer reset. Watchdog timer reset flag. 0: External hardware reset or power-on reset clears the flag. Flag can also be cleared by writing a 1. Flag survives if chip reset happened because of Watchdog timer overflow. 1: Hardware sets the flag on watchdog overflow. Watchdog timer refresh. 0: Hardware resets the bit when refresh is done. 1: Software sets the bit to force a Watchdog timer refresh. Start Watchdog timer. 0: Stop WDT. 1: Start WDT. WDFE WDRE WDTS WDT SWDT (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 22 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet Clock Option Register (COSR) Location BFH 7 6 5 4 3 2 1 0 Reset Value 00H COEN CO_SEL CO_IN Symbol COEN Function Clock Divider Enable 0: Disable Clock Divider 1: Enable Clock Divider Clock Divider Selection 00b: 1/4 clock source 01b: 1/16 clock source 10b: 1/256 clock source 11b: 1/1024 clock source Clock Source Selection 0b: Select clock from 1x clock 1b: Select clock from 2x clock The default value of this bit is set during Power-on reset by copying from Enable_Clock_Double_i non-volatile bit setting. CO_IN can be changed during normal operation to select the double clock option. If the clock source is a 1x clock, the clock divider exports 1/4, 1/16, 1/256, or 1/1024 of the input clock. If the clock source is a 2x clock, the clock divider exports 1/2, 1/8, 1/128, or 1/512 of the input clock. CO_SEL CO_IN Power Management Control Register (PMC) Location A1H 7 6 5 WDU 4 TCT 3 2 1 0 Reset Value xx000000b TCT2 PB2 PB1 UART Symbol WDU Function Watchdog Timer Clock Control 0:The clock for the Watchdog timer is running 1:The clock for the Watchdog timer is stopped Timer 0/1 Clock Control 0:The Timer 0/1 logic is running 1:The Timer 0/1 logic is stopped Timer 2 Clock Control 0:The Timer 2 logic is running 1:The Timer 2 logic is stopped Further Power Control 2 0:The PB2 logic is running 1:The PB2 logic is stopped Further Power Control 1 0:The PB1 logic is running 1:The PB1 logic is stopped Power consumption can be decreased by setting both PB2 and PB1 to 1. UART Clock Control 0:The UART logic is running 1:The UART logic is stopped TCT TCT2 PB2 PB1 UART (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 23 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet Watchdog Timer Data/Reload Register (WDTD) Location 85H 7 6 5 4 3 2 1 0 Reset Value 00H Watchdog Timer Data/Reload Power Control Register (PCON) Location 87H 7 SMOD1 6 SMOD0 5 4 POF 3 GF1 2 GF0 1 PD 0 IDL Reset Value 00x10000b Symbol SMOD1 SMOD0 Function Double Baud rate bit. If SMOD1 = 1, Timer 1 is used to generate the baud rate, and the serial port is used in modes 1, 2, and 3. FE/SM0 Selection bit. 0: SCON[7] = SM0 1: SCON[7] = FE, Power-on reset status bit, this bit will not be affected by any other reset. POF should be cleared by software. 0: No Power-on reset. 1: Power-on reset occurred General-purpose flag bit. General-purpose flag bit. Power-down bit, this bit is cleared by hardware after exiting from power-down mode. 0: Power-down mode is not activated. 1: Activates Power-down mode. Idle mode bit, this bit is cleared by hardware after exiting from idle mode. 0: Idle mode is not activated. 1: Activates idle mode. POF GF1 GF0 PD IDL (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 24 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet Serial Port Control Register (SCON) Location 98H 7 SM0/FE 6 SM1 5 SM2 4 REN 3 TB8 2 RB8 1 TI 0 RI Reset Value 00000000b Symbol FE Function Set SMOD0 = 1 to access FE bit. 0: No framing error 1: Framing Error. Set by receiver when an invalid stop bit is detected. This bit needs to be cleared by software. SMOD0 = 0 to access SM0 bit. Serial Port Mode Bit 0 Serial Port Mode Bit 1 SM0 0 0 1 SM1 0 1 0 Mode 0 1 2 Description Shift Register 8-bit UART 9-bit UART Baud Rate1 fOSC/6 (6 clock mode) or fOSC/12 (12 clock mode) Variable fOSC/32 or fOSC/16 (6 clock mode) or fOSC/64 or fOSC/32 (12 clock mode) Variable SM0 SM1 1 1 3 9-bit UART 1. fOSC = oscillator frequency SM2 Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then RI will not be set unless the received 9th data bit (RB8) is 1, indicating an address, and the received byte is a given or broadcast address. In Mode 1, if SM2 = 1 then RI will not be activated unless a valid stop bit was received. In Mode 0, SM2 should be 0. Enables serial reception. 0: to disable reception. 1: to enable reception. The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. In Modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. In Mode 0, RB8 is not used. Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission, Must be cleared by software. Receive interrupt flag. Set by hardware at the end of the8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software. REN TB8 RB8 TI RI (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 25 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet Timer/Counter 2 Control Register (T2CON) Location C8H 7 TF2 6 EXF2 5 RCLK 4 TCLK 3 EXEN2 2 TR2 1 C/T2# 0 CP/RL2# Reset Value 00H Symbol TF2 EXF2 Function Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK or TCLK = 1. Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1). Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflow to be used for the transmit clock. Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. Start/stop control for Timer 2. A logic 1 starts the timer. Timer or counter select (Timer 2) 0: Internal timer (OSC/6 in 6 clock mode, OSC/12 in 12 clock mode) 1: External event counter (falling edge triggered) Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# Timer/Counter 2 Mode Control (T2MOD) Location C9H 7 6 5 4 3 2 1 T2OE 0 DCEN Reset Value xxxxxx00b Symbol T2OE DCEN Function Not implemented, reserved for future use. Note: User should not write `1's to reserved bits. The value read from a reserved bit is indeterminate. Timer 2 Output Enable bit. Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter. (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 26 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet 4.0 FLASH MEMORY PROGRAMMING The device internal flash memory can be programmed or erased using In-Application Programming (IAP). 4.2.2 IAP Enable Bit The IAP enable bit, SFCF[6], enables In-Application programming mode. Until this bit is set, all flash programming IAP commands will be ignored. 4.2.3 IAP Mode Commands In order to protect the flash memory against inadvertent writes during unstable power conditions, all IAP commands need the following feed sequence to validate the execution of commands. Feed Sequence 1. Write A2H to SFIS0 (097H) 2. Write DFH to SFIS1 (0C4H) 32H 32H 43H 42H T4-1.1 1259 4.1 Product Identification The Read-ID command accesses the Signature Bytes that identify the device and the manufacturer as SST. External programmers primarily use these Signature Bytes in the selection of programming algorithms. TABLE 4-1: Product Identification Address Manufacturer's ID Device ID Device ID (extended) SST89E54RC SST89E52RC 30H 31H Data BFH F7H 3. Then write IAP command to SFCM (0B2H) Note: Above commands should be executed in sequence without interference from other instructions. All of the following commands can only be initiated in the IAP mode. In all situations, writing the control byte to the SFCM register will initiate all of the operations. A feed sequence is required prior to issuing commands through SFCM. Without the feed sequence all IAP commands are ignored. Sector-Erase, Byte-Program, and Byte-Verify commands will not be carried out on a specific memory page if the security locks are enabled on the memory page. The Byte-Program command is to update a byte of flash memory. If the original flash byte is not FFH, it should first be erased with an appropriate Erase command. Warning: Do not attempt to write (Program or Erase) to a sector that the code is currently fetching from. This will cause unpredictable program behavior and may corrupt program data. 4.2 In-Application Programming The device offers 17/9 KByte of in-application programmable flash memory. During In-Application Programming (IAP), the CPU of the microcontroller enters STOP mode. Upon completion of IAP the CPU will be released to , resume program execution. The mailbox registers (SFST, SFCM, SFAL, SFAH, SFDT and SFCF) located in the special function register (SFR), control and monitor the device's Erase and Program processes. Table 4-3 outlines the commands and their associated mailbox register settings. 4.2.1 IAP Mode Clock Source During IAP mode, both the CPU core and the flash controller unit are driven off the external clock. However, an internal oscillator will provide timing references for Program and Erase operations. The internal oscillator is only turned on when required, and is turned off as soon as the flash operation is completed. (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 27 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet 4.2.3.1 Chip-Erase The Chip-Erase command erases all bytes in both memory partitions. This command is only allowed when EA#=0 (external memory execution). Chip-Erase ignores the Security setting status and will erase all settings on all pages and the different chip-level security restrictions, returning the device to its Unlocked state. The Chip-Erase command will also erase the boot vector setting. Upon completion of Chip-Erase command, the chip will boot from the default setting. See Table 4-2 for the default boot vector setting. TABLE Device SST89E54RC SST89E52RC 4.2.3.2 Partition0-Erase The Partition0-Erase command erases all bytes in memory partition 0. All security bits associated with Page0-3 are also reset. IAP Enable ORL SFCF, #40H Set-Up MOV SFDT, #55H 4-2: Default Boot Vector Settings Address 4000H 2000H T4-2.1 1259 Feed Sequence MOV SFIS0, #A2H MOV SFIS1, #DFH Command Execution MOV SFCM, #0DH IAP Enable ORL SFCF, #40H SFCF[7] indicates operation completion 1259 F06.0 Set-Up MOV SFDT, #55H Feed Sequence MOV SFIS0, #A2H MOV SFIS1, #DFH 4.2.3.3 Sector-Erase The Sector-Erase command erases all of the bytes in a sector. The sector size for the flash memory blocks is 128 Bytes. The selection of the sector to be erased is determined by the contents of SFAH and SFAL. Command Execution MOV SFCM, #01H IAP Enable ORL SFCF, #40H SFCF[7] indicates operation completion 1259 F05.0 Program sector address MOV SFAH, #sector_addressH MOV SFAL, #sector_addressL Feed Sequence MOV SFIS0, #A2H MOV SFIS1, #DFH Command Execution MOV SFCM, #0BH SFCF[7] indicates operation completion 1259 F07.0 (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 28 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet 4.2.3.4 Byte-Program The Byte-Program command programs data into a single byte. The address is determined by the contents of SFAH and SFAL. The data byte is in SFDT. 4.2.3.6 Secure-Page0, Secure-Page1, SecurePage2, Secure-Page3, and Secure-Page4 Secure-Page0, Secure-Page1, Secure-Page2, SecurePage3, and Secure-Page4 commands are used to program the page security bits. Upon completion of any of these commands, the page security options will be updated immediately. Page security bits previously in un-programmed state can be programmed by these commands. The factory setting for these bits is all "1"s which indicates the pages are not security locked. IAP Enable ORL SFCF, #40H Program byte address MOV SFAH, #byte_addressH MOV SFAL, #byte_addressL Move data to SFDT MOV SFDT, #data Feed Sequence MOV SFIS0, #A2H MOV SFIS1, #DFH Command Execution MOV SFCM, #0EH SFCF[7] indicates operation completion 1259 F08.0 IAP Enable ORL SFCF, #40H Select Page Secure_Page0: MOV SFAH, #90H Secure_Page1: MOV SFAH, #91H Secure_Page2: MOV SFAH, #92H Secure_Page3: MOV SFAH, #93H Secure_Page4: MOV SFAH, #94H Feed Sequence MOV SFIS0, #A2H MOV SFIS1, #DFH 4.2.3.5 Byte-Verify The Byte-Verify command allows the user to verify that the device has correctly performed an Erase or Program command. Byte-Verify command returns the data byte in SFDT if the command is successful. The previous flash operation has to be fully completed before a Byte-Verify command can be issued. Command Execution MOV SFCM, #03H SFCF[7] indicates operation complete 1259 F10.0 IAP Enable ORL SFCF, #40H Program byte address MOV SFAH, #byte_addressH MOV SFAL, #byte_addressL Feed Sequence MOV SFIS0, #A2H MOV SFIS1, #DFH MOV SFCM, #0CH SFDT register contains data 1259 F09.0 (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 29 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet 4.2.3.7 Enable-Clock-Double Enable-Clock-Double command is used to make the MCU run at 6 clocks per machine cycle. The standard (default) is 12 clocks per machine cycle (i.e. clock double command disabled). IAP Enable ORL SFCF, #40H Set-up Enable-Clock-Double MOV SFAH, #E0H Feed Sequence MOV SFIS0, #A2H MOV SFIS1, #DFH Program Enable-Clock-Double Command Execution MOV SFCM, #08H SFCF[7] indicates operation complete 1259 F11.0 TABLE Operation 4-3: IAP COMMANDS SFCM [6:0] 01H 0DH 0BH 0EH 0CH 03H 03H 03H 03H 03H 05H 05H 05H 05H 08H 08H 08H 09H SFDT [7:0] 55H 55H X DI DO X X X X X X X X X X X X DI SFAH [7:0] X X AH AH AH 90H 91H 92H 93H 94H B0H B1H B2H B3H E0H E1H E2H F0H SFAL [7:0] X X AL AL AL X X X X X X X X X X X X X T4-3.0 1259 Chip-Erase Partition0-Erase Sector-Erase Byte-Program Byte-Verify (Read) Secure-Page0 Secure-Page1 Secure-Page2 Secure-Page3 Secure-Page4 Disable-Extern-IAP Disable-Extern-Boot Disable-Extern-MOVC Disable-Extern-Host-Cmd Enable-Clock-Double Boot-From-User-Vector Boot-From-Zero Set-User-Boot-Vector Note: VIL = Input Low Voltage; VIH = Input High Voltage; VIH1 = Input High Voltage (XTAL, RST); X = Don't care; AL = Address low order byte; AH = Address high order byte; DI = Data Input; DO = Data Output. 4.3 In-System Programming SST provides an example In-System Programming (ISP) solution for this device series. An example bootstrap loader can be pre-programmed into Partition1 to demonstrate the initial user program code loading or subsequent user code updating via the IAP operation. (c)2007 Silicon Storage Technology, Inc. Users can either use the SST ISP solution or develop a customized ISP solution. Customized ISP firmware can be pre-programmed into a user-defined boot vector. See Section "Boot Sequence" on page 40 for details. S71259-04-000 1/07 30 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet 5.0 TIMERS/COUNTERS 5.1 Timers The device has three 16-bit registers that can be used as either timers or event counters. The three timers/counters are denoted Timer 0 (T0), Timer 1 (T1), and Timer 2 (T2). Each is designated a pair of 8-bit registers in the SFRs. The pair consists of a most significant (high) byte and least significant (low) byte. The respective registers are TL0, TH0, TL1, TH1, TL2, and TH2. TABLE 5-2: Timer/Counter 1 TMOD Mode 0 Used as Timer 1 2 3 0 Used as Counter 1 2 3 Function 13-bit Timer 16-bit Timer 8-bit Auto-Reload Does not run 13-bit Timer 16-bit Timer 8-bit Auto-Reload Not available Internal Control1 00H 10H 20H 30H 40H 50H 60H External Control2 80H 90H A0H B0H C0H D0H E0H T5-2.0 1259 5.2 Timer Set-up Refer to Table 3-7 for TMOD, TCON, and T2CON registers regarding timers T0, T1, and T2. The following tables provide TMOD values to be used to set up Timers T0, T1, and T2. Except for the baud rate generator mode, the values given for T2CON do not include the setting of the TR2 bit. Therefore, bit TR2 must be set separately to turn the timer on. TABLE 5-1: Timer/Counter 0 TMOD Mode 0 Used as Timer 1 2 3 0 Used as Counter 1 2 3 Function 13-bit Timer 16-bit Timer 8-bit Auto-Reload Two 8-bit Timers 13-bit Timer 16-bit Timer 8-bit Auto-Reload Two 8-bit Timers Internal Control1 00H 01H 02H 03H 04H 05H 06H 07H External Control2 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH T5-1.0 1259 1. The Timer is turned ON/OFF by setting/clearing bit TR1 in the software. 2. The Timer is turned ON/OFF by the 1 to 0 transition on INT1# (P3.3) when TR1 = 1 (hardware control). TABLE 5-3: Timer/Counter 2 T2CON Mode 16-bit Auto-Reload 16-bit Capture Internal Control1 00H 01H 34H External Control2 08H 09H 36H Used as Timer Baud rate generator receive and transmit same baud rate Receive only Transmit only 24H 14H 02H 03H 26H 16H 0AH 0BH T5-3.0 1259 Used as Counter 16-bit Auto-Reload 16-bit Capture 1. The Timer is turned ON/OFF by setting/clearing bit TR0 in the software. 2. The Timer is turned ON/OFF by the 1 to 0 transition on INT0# (P3.2) when TR0 = 1 (hardware control). 1. Capture/Reload occurs only on timer/counter overflow. 2. Capture/Reload occurs on timer/counter overflow and a 1 to 0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate generating mode. (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 31 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet 5.3 Programmable Clock-Out A 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed: 1. to input the external clock for Timer/Counter 2, or 2. to output a 50% duty cycle clock ranging from 122 Hz to 8 MHz at a 16 MHz operating frequency (61 Hz to 4 MHz in 12 clock mode). To configure Timer/Counter 2 as a clock generator, bit C/#T2 (in T2CON) must be cleared and bit T20E in T2MOD must be set. Bit TR2 (T2CON.2) also must be set to start the timer. The Clock-Out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L) as shown in this equation: Oscillator Frequency n x (65536 - RCAP2H, RCAP2L) n= 2 (in 6 clock mode) 4 (in 12 clock mode) 6.0 SERIAL I/O 6.1 Full-Duplex, Enhanced UART The device serial I/O port is a full-duplex port that allows data to be transmitted and received simultaneously in hardware by the transmit and receive registers, respectively, while the software is performing other tasks. The transmit and receive registers are both located in the Serial Data Buffer (SBUF) special function register. Writing to the SBUF register loads the transmit register, and reading from the SBUF register obtains the contents of the receive register. The UART has four modes of operation which are selected by the Serial Port Mode Specifier (SM0 and SM1) bits of the Serial Port Control (SCON) special function register. In all four modes, transmission is initiated by any instruction that uses the SBUF register as a destination register. Reception is initiated in mode 0 when the Receive Interrupt (RI) flag bit of the Serial Port Control (SCON) SFR is cleared and the Reception Enable/ Disable (REN) bit of the SCON register is set. Reception is initiated in the other modes by the incoming start bit if the REN bit of the SCON register is set. 6.1.1 Framing Error Detection Framing Error Detection is a feature, which allows the receiving controller to check for valid stop bits in modes 1, 2, or 3. Missing stops bits can be caused by noise in serial lines or from simultaneous transmission by two CPUs. Framing Error Detection is selected by going to the PCON register and changing SMOD0 = 1 (see Figure 6-1). If a stop bit is missing, the Framing Error bit (FE) will be set. Software may examine the FE bit after each reception to check for data errors. After the FE bit has been set, it can only be cleared by software. Valid stop bits do not clear FE. When FE is enabled, RI rises on the stop bit, instead of the last data bit (see Figure 6-2 and Figure 6-3). Where (RCAP2H, RCAP2L) = the contents of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. In the Clock-Out mode, Timer 2 roll-overs will not generate an interrupt. This is similar to when it is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and the Clock-Out frequency will not be the same. (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 32 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet SM0/FE SM1 SM2 REN TB8 RB8 TI RI SCON (98H) Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1) SM0 to UART mode control (SMOD0 = 0) SMOD1 SMOD0 BOF POF GF1 GF0 PD IDL PCON (87H) To UART framing error control 1259 F12.0 FIGURE 6-1: Framing Error Block Diagram RXD D0 Start bit D1 D2 D3 D4 D5 D6 D7 Stop bit Data byte RI SMOD0=X FE SMOD0=1 1259 F13.0 FIGURE 6-2: UART Timings in Mode 1 RXD D0 Start bit D1 D2 D3 D4 D5 D6 D7 D8 Ninth bit Stop bit Data byte RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 1259 F14.0 FIGURE 6-3: UART Timings in Modes 2 and 3 (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 33 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet 6.1.2 Automatic Address Recognition Automatic Address Recognition helps to reduce the MCU time and power required to talk to multiple serial devices. Each device is hooked together sharing the same serial link with its own address. In this configuration, a device is only interrupted when it receives its own address, thus eliminating the software overhead to compare addresses. This same feature helps to save power because it can be used in conjunction with idle mode to reduce the system's overall power consumption. Since there may be multiple slaves hooked up serial to one master, only one slave would have to be interrupted from idle mode to respond to the master's transmission. Automatic Address Recognition (AAR) allows the other slaves to remain in idle mode while only one is interrupted. By limiting the number of interruptions, the total current draw on the system is reduced. There are two ways to communicate with slaves: a group of them at once, or all of them at once. To communicate with a group of slaves, the master sends out an address called the given address. To communicate with all the slaves, the master sends out an address called the "broadcast" address. AAR can be configured as mode 2 or 3 (9-bit modes) and setting the SM2 bit in SCON. Each slave has its own SM2 bit set waiting for an address byte (9th bit = 1). The Receive Interrupt (RI) flag will only be set when the received byte matches either the given address or the broadcast address. Next, the slave then clears its SM2 bit to enable reception of the data bytes (9th bit = 0) from the master. When the 9th bit = 1, the master is sending an address. When the 9th bit = 0, the master is sending actual data. If mode 1 is used, the stop bit takes the place of the 9th bit. Bit RI is set only when the received command frame address matches the device's address and is terminated by a valid stop bit. Note that mode 0 cannot be used. Setting SM2 bit in the SCON register in mode 0 will have no effect. Each slave's individual address is specified by SFR SADDR. SFR SADEN is a mask byte that defines "don't care" bits to form the given address when combined with SADDR. See the example below: Slave 1 SADDR = SADEN = GIVEN 1111 0001 1111 1010 Slave 3 SADDR = 1111 1001 SADEN = 1111 0101 GIVEN = 1111 X0X1 Slave 2 SADDR = SADEN = GIVEN 1111 0011 1111 1001 = 1111 0XX1 6.1.2.1 Using the Given Address to Select Slaves Any bits masked off by a 0 from SADEN become a "don't care" bit for the given address. Any bit masked off by a 1, becomes ANDED with SADDR. The "don't cares" provide flexibility in the user-defined addresses to address more slaves when using the given address. Shown in the example above, Slave 1 has been given an address of 1111 0001 (SADDR). The SADEN byte has been used to mask off bits to a given address to allow more combinations of selecting Slave 1 and Slave 2. In this case for the given addresses, the last bit (LSB) of Slave 1 is a "don't care" and the last bit of Slave 2 is a 1. To communicate with Slave 1 and Slave 2, the master would need to send an address with the last bit equal to 1 (e.g. 1111 0001) since Slave 1's last bit is a don't care and Slave 2's last bit has to be a 1. To communicate with Slave 1 alone, the master would send an address with the last bit equal to 0 (e.g. 1111 0000), since Slave 2's last bit is a 1. See the table below for other possible combinations. Select Slave 1 Only Slave 1 Given Address 1111 0X0X Possible Addresses 1111 0000 1111 0100 Select Slave 2 Only Slave 2 Given Address 1111 0XX1 Possible Addresses 1111 0111 1111 0011 Select Slaves 1 and 2 Slaves 1 and 2 Possible Addresses 1111 0001 1111 0101 If the user added a third slave such as the example below: = 1111 0X0X (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 34 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet Select Slave 3 Only Slave 2 Given Address 1111 X0X1 Possible Addresses 1111 1011 1111 1001 6.1.2.2 Using the Broadcast Address to Select Slaves Using the broadcast address, the master can communicate with all the slaves at once. It is formed by performing a logical OR of SADDR and SADEN with 0s in the result treated as "don't cares". Slave 1 1111 0001 = SADDR +1111 1010 = SADEN 1111 1X11 = Broadcast The user could use the possible addresses above to select slave 3 only. Another combination could be to select slave 2 and 3 only as shown below. Select Slaves 2 and 3 Only Slaves 2 and 3 Possible Addresses 1111 0011 More than one slave may have the same SADDR address as well, and a given address could be used to modify the address so that it is unique. "Don't cares" allow for a wider range in defining the broadcast address, but in most cases, the broadcast address will be FFH. On reset, SADDR and SADEN are "0". This produces an given address of all "don't cares" as well as a broadcast address of all "don't cares." This effectively disables Automatic Addressing mode and allows the microcontroller to function as a standard 8051, which does not make use of this feature. (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 35 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet 7.0 WATCHDOG TIMER The programmable Watchdog Timer (WDT) is for fail safe protection against software deadlock and for automatic recovery. The Watchdog timer can be utilized as a watchdog or a timer. To use the Watchdog timer as a watchdog, WDRE (WDTC[3]) should be set to "1." To use the Watchdog timer as a timer only, WDRE should be set to "0" so that an interrupt will be generated upon timer overflow, and the EWD (IEA[6]) should be set to "1" in order to enable the interrupt. 7.3 Clock Source The WDT in the device uses the system clock (XTAL1) as its time base. So strictly speaking, it is a watchdog counter rather than a Watchdog timer. The WDT register will increment every 344,064 crystal clocks. The upper 8-bits of the time base register (WDTD) are used as the reload register of the WDT. Figure 7-1 provides a block diagram of the WDT. Two SFRs (WDTC and WDTD) control Watchdog timer operation. The time-out period of the WDT is calculated as follows: Period = (255 - WDTD) * 344064 * 1/fCLK (XTAL1) where WDTD is the value loaded into the WDTD register and fOSC is the oscillator frequency. 7.1 Watchdog Timer Mode To protect the system against software deadlock, WDT (WDTC[1]) should be refreshed within a user-defined time period. Without a periodic refresh, an internal hardware reset will be initiated when WDRE (WDTC[3]) = 1). The WDRE bit can only be cleared by a power-on reset. Any Write to WDTC must be preceded by a correct feed sequence. If WDTON (WDTC[6])=0, SWDT (WDTC[0]) controls the start or stop of the watchdog. If WDTON = 1, the watchdog starts regardless of SWDT and cannot be stopped. The upper 8 bits of the time base register (WDTD) is used as the reload register of the counter. When WDT (WDTC[1]) is set to "1," the content of WDTD is loaded into the watchdog counter and the prescaler is also cleared. If a watchdog reset occurs, the internal reset is active for at least one watchdog clock cycle. The code execution will begin immediately after the reset cycle. The WDTS flag bit is set by Watchdog timer overflow and can only be cleared by power-on reset. Users can also clear the WDTS bit by writing "1" to it following a correct feed sequence. 7.4 Feed Sequence In Watchdog mode (WDRE=1), a feed sequence is needed to write into the WDTC register. The correct feed sequence is: 1. write FDH to SFIS1, 2. write 2AH to SFIS0, then 3. write to the WDTC register An incorrect feed sequence will cause an immediate reset in Watchdog mode. In Timer mode, the WDTC and WDTD can be written at any time. A feed sequence is not required. 7.5 Power Saving Considerations for Using the Watchdog Timer During Idle mode, the Watchdog timer will remain active. The device should be awakened and the Watchdog timer refreshed periodically before expiration. During Powerdown mode, the Watchdog timer is stopped. When the Watchdog timer is used as a pure timer, users can turn off the clock to save power. See "Power Management Control Register (PMC)" on page 23. 7.2 Pure Timer Mode In Timer mode, the WDTC and WDTD can be written at any time without a feed sequence. Setting or clearing the SWDT bit will start or stop the counter. A timer overflow will set the WDTS bit. Writing "1" to this bit clears the bit. When an overflow occurs, the content of WDTD is reloaded into the counter and the Watchdog timer immediately begins to count again. If the interrupt is enabled, an interrupt will occur when the timer overflows. The vector address is 053H and it has a second level priority by default. A feed sequence is not required in this mode. (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 36 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet CLK (XTAL1) Counter 344064 clks WDT Upper Byte WDT Reset Internal Reset Ext. RST WDTC WDTD 1259 F18.0 FIGURE 7-1: Block Diagram of Programmable Watchdog Timer (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 37 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet 8.0 SECURITY LOCK The security lock protects against software piracy and prevents the contents of the flash from being read by unauthorized parties. It also protects against code corruption resulting from accidental erasing and programming to the internal flash memory. There are two different types of security locks in the device security lock system: ChipLevel Security Lock and Page-Level Security Lock. 8.1.3 Disable Boot From External Memory When Disable-Extern-Boot command is executed either by External Host Mode Command or IAP Mode Command, the EA pin value will be ignored during chip Reset and always boot from the internal memory. 8.1.4 Disable External IAP Commands When Disable-Extern-IAP command is executed either by External Host Mode Command or IAP Mode Command, all IAP commands executed from external memory are disabled except Chip-Erase command. All IAP commands executed from internal memory are allowed if the Page Lock is not set. 8.1 Chip-Level Security Lock There are four types of chip-level security locks. 1. Disable External MOVC instruction 2. Disable External Host Mode (Except Read Chip ID and Chip-Erase commands) 3. Disable Boot from External Memory 4. Disable External IAP commands (Except ChipErase commands) Users can turn on these security locks in any combination to achieve the security protection scheme. To unlock security locks, the Chip-Erase command must be used. 8.1.1 Disable External MOVC instruction When Disable-Extern-MOVC command is executed either by External Host Mode command or IAP Mode Command, MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory. 8.1.2 Disable External Host Mode When Disable-Extern-Host-Cmd command is executed either by External Host Mode Command or IAP Mode Command, all external host mode commands are disabled except Chip-Erase command and Read-ID command. Upon activation of this option, the device can not be accessed through external host mode. User can not verify and copy the contents of the internal flash 8.2 Page-Level Security Lock When any of Secure-Page0, Secure-Page1, SecurePage2, Secure-Page3, or Secure-Page4 command is executed, the individual page (Page0, Page1, Page2, Page3, or Page4) will enter secured mode. No part of the page can be verified by either External Host mode commands or IAP commands. MOVC instructions are also unable to read any data from the page. To unlock the security locks on Page0-3 of the primary partition (Partition0), the Partition0-Erase command must be used. To unlock the security lock on Page4, the Chip-Erase command must be used. 8.3 Read Operation Under Lock Condition The following three cases can be used to indicate the Read operation is targeting a locked, secured memory area: 1. External host mode: Read-back = 55H (locked) 2. IAP command: Read-back = previous SFDT data 3. MOVC: Read-back = 00H (blank) (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 38 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet 9.0 RESET A system reset initializes the MCU and begins program execution at program memory location 0000H or the boot vector address. The reset input for the device is the RST pin. In order to reset the device, a logic level high must be applied to the RST pin for at least two machine cycles (24 clocks), after the oscillator becomes stable. ALE and PSEN# are weakly pulled high during reset. During reset, ALE and PSEN# output a high level in order to perform a proper reset. This level must not be affected by external element. A system reset will not affect the 512 Bytes of onchip RAM while the device is running, however, the contents of the on-chip RAM during power up are indeterminate. Following reset, all Special Function Registers (SFR) return to their reset values outlined in Tables 3-3 to 3-8. For a low frequency oscillator with slow start-up time the reset signal must be extended in order to account for the slow start-up time. This method maintains the necessary relationship between VDD and RST to avoid programming at an indeterminate location. The POF flag in the PCON register is set to indicate an initial power up condition. The POF flag will remain active until cleared by software. Please refer to Section 3.5, PCON register definition, for detailed information. For more information on system level design techniques, please review the Design Considerations for the SST FlashFlex Family Microcontroller application note. 9.1 Power-on Reset At initial power up, the port pins will be in a random state until the oscillator has started and the internal reset algorithm has weakly pulled all pins high. When power is applied to the device, the RST pin must be held high long enough for the oscillator to start up (usually several milliseconds for a low frequency crystal), in addition to two machine cycles for a valid power-on reset. An example of a method to extend the RST signal is to implement a RC circuit by connecting the RST pin to VDD through a 10 F capacitor and to VSS through an 8.2K resistor as shown in Figure 9-1. Note that if an RC circuit is being used, provisions should be made to ensure the VDD rise time does not exceed 1 millisecond and the oscillator startup time does not exceed 10 milliseconds. VDD + 10F RST 8.2K C2 XTAL2 VDD SST89E54RC SST89E52RC XTAL1 C1 1259 F25.2 FIGURE 9-1: Power-on Reset Circuit (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 39 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet 9.2 Boot Sequence After Power On Reset, the device can boot from one of three locations: zero, default boot vector (see Table 4-2), or a user-defined boot vector. The checking sequence follows the flowchart in Figure 9-2. If the device uses external code memory (EA#=0), the boot-start address is always zero. The next sequence is to detect any external hardware pin setup. The device should check P1[0] and P1[1] at the falling edge of reset. (See Figure 9-3 for the timing diagram.) If both pins are low, the device is forced to boot from either the default boot vector or the user-defined boot vector depending on the setting of Boot_From_User_Vector_i. The Boot_Status_Flag bit (HWIAP) in the SFCF register indiTABLE Device SST89E54RC SST89E52RC cates whether or not the system booted with P1[0] and P1[1] set to low during reset. (See Section 3.5, "Special Function Registers" on page 11 for details.) Programming the control bits (Boot_From_User_Vector_i and Boot_From_Zero_i) can be done through IAP mode commands or External Host Mode commands. The factory default setting for these two bits is "1" and will lead the system to boot from the default boot vector per Table 4-2. When the device is configured to boot from a user-defined vector, users should use the Set_User_Boot_Vector command to program the Boot Vector[7:0]. The final boot vector address is calculated in Table 9-1. 9-1: Boot Vector Address Bit Number 15 0 0 14 0 0 0 13 12 11 10 9 8 7 6 5 0 4 0 0 3 0 0 2 0 0 1 0 0 0 0 0 T9-1.1 1259 Boot Vector[7:0] Boot Vector[7:0] Power on Reset Yes Boot from External EA# P1.0 300 Clk 300 Clk No P1.1 Both P1.0 and P1.1 are low? Yes 1259 F26.0 FIGURE No 9-3: Hardware Pin Setup Yes Boot_From_Zero_i bit cleared? (=0) No 9.3 Interrupt Priority and Polling Sequence The device supports seven interrupt sources under a four level priority scheme. Table 9-2 and Figure 9-4 summarize the polling sequence of the supported interrupts. Yes Boot_From_User_Vector_i bit cleared? (=0) No Address 0 Default Boot Vector 1259 FC_Boot_Seq.0 FIGURE 9-2: Boot Sequence Flowchart (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 40 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet IE & IEA Registers 0 INT0# 1 IT0 IE0 IP/IPH/IPA/IPAH Registers Highest Priority Interrupt Watchdog Timer Interrupt Polling Sequence TF0 0 INT1# 1 IT1 IE1 TF1 RI TI TF2 EXF2 Individual Enables Global Disable 1259 F27.0 Lowest Priority Interrup 1259 F27.0 FIGURE 9-4: Interrupt Sequence (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 41 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet TABLE 9-2: Interrupt Polling Sequence Interrupt Flag IE0 TF0 IE1 TF1 TI/RI TF2, EXF2 Vector Address 0003H 0053H 000BH 0013H 001BH 0023H 002BH Interrupt Enable EX0 EWD ET0 EX1 ET1 ES ET2 Interrupt Priority PX0/H PWD/H PT0/H PX1/H PT1/H PS/H PT2/H Service Priority 1(highest) 2 3 4 5 6 7 Wake-Up Power-down yes no no yes no no no T9-2.0 1259 Description Ext. Int0 Watchdog T0 Ext. Int1 T1 UART T2 (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 42 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet 10.0 POWER-SAVING MODES The device provides two power saving modes of operation for applications where power consumption is critical. The two modes are idle and power-down, see Table 10-1. In addition to these two power saving modes, users can choose to set the device to run at one of four slower clock rates to reduce power consumption. See Section 11.3, "Clock Divider Option". Another option is to turn off the clocks by individual functional blocks, please refer to Section 3.5, the PMC register definition, for detailed information. 10.2 Power-down Mode The power-down mode is entered by setting the PD bit in the PCON register. In the power-down mode, the clock is stopped and external interrupts are active for level sensitive interrupts only. SRAM contents are retained during powerdown, the minimum VDD level is 2.0V. The device exits power-down mode through either an enabled external level sensitive interrupt or a hardware reset. The start of the interrupt clears the PD bit and exits power-down. Holding the external interrupt pin low restarts the oscillator, the signal must hold low at least 1024 clock cycles before bringing back high to complete the exit. Upon interrupt signal restored to logic VIH, the interrupt service routine program execution resumes beginning at the instruction immediately following the instruction which invoked power-down mode. A hardware reset starts the device similar to power-on reset. To exit properly out of power-down, the reset or external interrupt should not be executed before the VDD line is restored to its normal operating voltage. Be sure to hold VDD voltage long enough at its normal operating level for the oscillator to restart and stabilize (normally less than 10 ms). 10.1 Idle Mode Idle mode is entered setting the IDL bit in the PCON register. In idle mode, the program counter (PC) is stopped. The system clock continues to run and all interrupts and peripherals remain active. The on-chip RAM and the special function registers hold their data during this mode. The device exits idle mode through either a system interrupt or a hardware reset. Exiting idle mode via system interrupt, the start of the interrupt clears the IDL bit and exits idle mode. After exit the Interrupt Service Routine, the interrupted program resumes execution beginning at the instruction immediately following the instruction which invoked the idle mode. A hardware reset starts the device similar to a power-on reset. TABLE Mode Idle 10-1: Power Saving Modes Initiated by State of MCU CLK is running. Interrupts, serial port and timers/counters are active. Program Counter is stopped. ALE and PSEN# signals at a HIGH level during Idle. All registers remain unchanged. Exited by Enabled interrupt or hardware reset. Start of interrupt clears IDL bit and exits idle mode, after the ISR RETI instruction, program resumes execution beginning at the instruction following the one that invoked idle mode. A user could consider placing two or three NOP instructions after the instruction that invokes idle mode to eliminate any problems. A hardware reset restarts the device similar to a power-on reset. Enabled external level sensitive interrupt or hardware reset. Start of interrupt clears PD bit and exits power-down mode, after the ISR RETI instruction program resumes execution beginning at the instruction following the one that invoked power-down mode. A user could consider placing two or three NOP instructions after the instruction that invokes power-down mode to eliminate any problems. A hardware reset restarts the device similar to a power-on reset. T10-1.0 1259 Software * (Set IDL bit in PCON) * MOV PCON, #01H; * * * Power-down Software * (Set PD bit in PCON) * MOV PCON, #02H; * * CLK is stopped. On-chip SRAM and SFR data is maintained. ALE and PSEN# signals at a LOW level during power -down. External Interrupts are only active for level sensitive interrupts, if enabled. (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 43 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet 11.0 SYSTEM CLOCK AND CLOCK OPTIONS 11.1 Clock Input Options and Recommended Capacitor Values for Oscillator Shown in Figure 11-1 are the input and output of an internal inverting amplifier (XTAL1, XTAL2), which can be configured for use as an on-chip oscillator. When driving the device from an external clock source, XTAL2 should be left disconnected and XTAL1 should be driven. At start-up, the external oscillator may encounter a higher capacitive load at XTAL1 due to interaction between the amplifier and its feedback capacitance. However, the capacitance will not exceed 15 pF once the external signal meets the VIL and VIH specifications. Crystal manufacturer, supply voltage, and other factors may cause circuit performance to differ from one application to another. C1 and C2 should be adjusted appropriately for each design. Table 11-1, shows the typical values for C1 and C2 vs. crystal type for various frequencies TABLE 11-1:Recommended Values for C1 and C2 by Crystal Type Crystal Quartz Ceramic C1 = C2 20-30pF 40-50pF T11-1.1 1259 More specific information about on-chip oscillator design can be found in the FlashFlex Oscillator Circuit Design Considerations application note. 11.2 Clock Doubling Option By default, the device runs at 12 clocks per machine cycle (x1 mode). The device has a clock doubling option to speed up to 6 clocks per machine cycle. Please refer to Table 11-2 for detail. Clock double mode can be enabled either via the external host mode or the IAP mode. Please refer to Table 4-3 for the IAP mode enabling command (When set, the EnableClock-Double_i bit in the SFST register will indicate 6-clock mode.). The clock double mode is only for doubling the internal system clock and the internal flash memory, i.e. EA#=1. To access the external memory and the peripheral devices, careful consideration must be taken. Also note that the crystal output (XTAL2) will not be doubled. 11.3 Clock Divider Option The device has an option to run at scaled-down clock rates of 1/4, 1/16, 1/256, and 1/1024. The COEN bit in the COSR register must be set to enable this option. The CO_SEL bits are set to select the clock rate. See the COSR register for more information. XTAL2 C2 C1 XTAL1 VSS External Oscillator Signal NC XTAL2 XTAL1 VSS Using the On-Chip Oscillator External Clock Drive 1259 F28.0 FIGURE TABLE Device 11-1: Oscillator Characteristics 11-2: Clock Doubling Features Standard Mode (x1) Clocks per Machine Cycle Max. External Clock Frequency (MHz) Clock Double Mode (x2) Clocks per Machine Cycle Max. External Clock Frequency (MHz) SST89E5xRC 12 33 6 16 T11-2.0 1259 (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 44 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet 12.0 ELECTRICAL SPECIFICATION Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Ambient Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Voltage on EA# Pin to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +14.0V D.C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20ns) on Any Other Pin to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD+1.0V Maximum IOL per I/O Pins P1.5, P1.6, P1.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Maximum IOL per I/O for All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA Package Power Dissipation Capability (TA = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5W Through Hole Lead Soldering Temperature (10 Seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C Surface Mount Solder Reflow Temperature1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C for 10 seconds Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Excluding certain with-Pb 32-PLCC units, all packages are 260C capable in both non-Pb and with-Pb solder versions. Certain with-Pb 32-PLCC package types are capable of 240C for 10 seconds; please consult the factory for the latest information. 2. Outputs shorted for no more than one second. No more than one output shorted at a time. (Based on package heat transfer limitations, not device power consumption. Note: This specification contains preliminary information on new products in production. The specifications are subject to change without notice. TABLE Symbol TA VDD fOSC 12-1: Operating Range Description Ambient Temperature Under Bias Standard Supply Voltage SST89E5xRC Oscillator Frequency SST89E5xRC Oscillator Frequency for In-Application programming SST89E5xRC .25 33 MHz T12-1.1 1259 Min. 0 4.5 0 Max +70 5.5 33 Unit C V MHz TABLE Symbol NEND TDR1 ILTH1 1 12-2: Reliability Characteristics Parameter Endurance Data Retention Latch Up Minimum Specification 10,000 100 100 + IDD Units Cycles Years mA Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78 T12-2.0 1259 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 45 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet TABLE 12-3: AC Conditions of Test Input Rise/Fall Time . . . . . . . . . . . . . . . 10 ns Output Load . . . . . . . . . . . . . . . . . . . . . CL = 100 pF See Figures 12-6 and 12-8 T12-3.0 1259 TABLE Symbol TPU-READ 12-4: Recommended System Power-up Timings Parameter 1 Minimum 100 100 Units s s T12-4.2 1259 Power-up to Read Operation Power-up to Write Operation TPU-WRITE1 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter TABLE CI/O1 CIN 1 12-5: Pin Impedance (TA=25 C, f=1 Mhz, other pins open) Description I/O Pin Capacitance Input Capacitance Pin Inductance Test Condition VI/O = 0V VIN = 0V Maximum 15 pF 12 pF 20 nH T12-5.4 1259 Parameter LPIN2 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. Refer to PCI spec. (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 46 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet 12.1 DC Electrical Characteristics TABLE Symbol VIL VIH VIH1 VOL VOL 12-6: DC Characteristics for SST89E5xRC: TA = -0C to +70C; VDD = 4.5-5.5V; VSS = 0V Parameter Input Low Voltage Input High Voltage Input High Voltage (XTAL1, RST) Output Low Voltage (Ports 1.5, 1.6, 1.7) Output Low Voltage (Ports 1, 2, 3)1 Test Conditions 4.5 < VDD < 5.5 4.5 < VDD < 5.5 4.5 < VDD < 5.5 VDD = 4.5V IOL = 16mA VDD = 4.5V IOL = 100A2 IOL = 1.6mA2 IOL = 3.5mA2 0.3 0.45 1.0 0.3 0.45 VDD - 0.3 VDD - 0.7 VDD - 1.5 VDD - 0.3 VDD - 0.7 -75 -650 10 40 @ 1 MHz, 25C 225 15 32 26 TA = 0C to 70C 50 V V V V V V V V V V A A A K pF mA mA A T12-6.1 1259 Min -0.5 0.2VDD + 0.9 0.7VDD Max 0.2VDD - 0.1 VDD + 0.5 VDD + 0.5 1.0 Units V V V V VOL1 Output Low Voltage (Port 0, ALE, PSEN#)1,3 VDD = 4.5V IOL = 200A2 IOL = 3.2mA2 VOH Output High Voltage (Ports 1, 2, 3, ALE, PSEN#)4 VDD = 4.5V IOH = -10A IOH = -30A IOH = -60A VOH1 Output High Voltage (Port 0 in External Bus Mode)4 VDD = 4.5V IOH = -200A IOH = -3.2mA IIL ITL ILI RRST CIO IDD Logical 0 Input Current (Ports 1, 2, 3) Logical 1-to-0 Transition Current (Ports 1, 2, 3)5 Input Leakage Current (Port 0) RST Pull-down Resistor Pin Capacitance6 Power Supply Current Active Mode @ 33 MHz Idle Mode@ 33 MHz Power-down Mode (min VDD = 2V) VIN = 0.4V VIN = 2V 0.45 < VIN < VDD-0.3 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: 15mA Maximum IOL per port pin: Maximum IOL per 8-bit port: 26mA Maximum IOL total for all outputs:71mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Capacitive loading on Ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and Ports 1 and 3. The noise due to external bus capacitance discharging into the Port 0 and 2 pins when the pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. 3. Load capacitance for Port 0, ALE and PSEN#= 100pF, load capacitance for all other outputs = 80 pF. 4. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN# to momentarily fall below the VDD - 0.7 specification when the address bits are stabilizing. 5. Pins of Ports 1, 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 6. Pin capacitance is characterized but not tested. EA# is 25pF (max). (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 47 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet 12.2 AC Electrical Characteristics AC Characteristics: (Over Operating Conditions: Load Capacitance for Port 0, ALE#, and PSEN# = 100pF; Load Capacitance for All Other Outputs = 80pF) TABLE 12-7: AC Electrical Characteristics TA = -0C to +70C, VDD = 4.5-5.5V@33MHz, VSS = 0V Oscillator 25 MHz (x1 Mode) 12 MHz (x2 Mode)1 Symbol Parameter Min 0 0 65 Max 25 12 33 MHz (x1 Mode) 16 MHz (x2 Mode)1 Min 0 0 46 15 15 66 15 76 41 0 15 32 10 152 152 102 0 0 49 192 198 76 91 20 10 162 0 15 0 45 TCLCL - 15 (5V) 10 106 3TCLCL - 15 (5V) 4TCLCL - 30 (5V) TCLCL - 20 TCLCL - 20 (5V) 7TCLCL - 50 (5V) 0 TCLCL + 15 (5V) 0 2TCLCL - 12 (5V) 8TCLCL - 50 (5V) 9TCLCL - 75 (5V) 3TCLCL + 15 (5V) 22 92 10 6TCLCL - 30 (5V) 6TCLCL - 30 (5V) 5TCLCL - 50 (5V) TCLCL - 8 5TCLCL - 60 (5V) 10 TCLCL - 15 (5V) TCLCL - 15 (5V) 3TCLCL - 15 (5V) 3TCLCL - 50 (5V) Max 33 16 Min 0 0 2TCLCL - 15 TCLCL - 15 (5V) TCLCL - 15 (5V) 4TCLCL - 45 (5V) Variable Max Units MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns T12-7.0 1259 1/TCLCL 1/2TCLCL TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TPXAV TAVIV TPLAZ TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TWHQX TQVWH TRLAZ TWHLH x1 Mode Oscillator Frequency x2 Mode Oscillator Frequency ALE Pulse Width Address Valid to ALE Low Address Hold After ALE Low ALE Low to Valid Instr In ALE Low to PSEN# Low PSEN# Pulse Width PSEN# Low to Valid Instr In Input Instr Hold After PSEN# Input Instr Float After PSEN# PSEN# to Address valid Address to Valid Instr In PSEN# Low to Address Float RD# Pulse Width Write Pulse Width (WE#) RD# Low to Valid Data In Data Hold After RD# Data Float After RD# ALE Low to Valid Data In Address to Valid Data In ALE Low to RD# or WR# Low Address to RD# or WR# Low Data Valid to WR# High to Low Transition Data Hold After WR# Data Valid to WR# High RD# Low to Address Float RD# to WR# High to ALE High 1. Calculated values are for x1 Mode only (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 48 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet Explanation of Symbols Each timing symbol has 5 characters. The first character is always a `T' (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. A: C: D: H: I: L: P: Address Clock Input data Logic level HIGH Instruction (program memory contents) Logic level LOW or ALE PSEN# Q: R: T: V: W: X: Z: Output data RD# signal Time Valid WR# signal No longer a valid logic level High Impedance (Float) For example: TAVLL = Time from Address Valid to ALE Low TLLPL = Time from ALE Low to PSEN# Low (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 49 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet TLHLL ALE TAVLL TLLPL TPLAZ TLLAX TLLIV TPLIV TPXAV TPXIZ TPXIX INSTR IN A0 - A7 TPLPH PSEN# PORT 0 A0 - A7 TAVIV PORT 2 A8 - A15 A8 - A15 1259 F31.0 FIGURE 12-1: External Program Memory Read Cycle TLHLL ALE TWHLH PSEN# TLLDV TRLRH TLLWL RD# TAVLL TLLAX TRLAZ TRLDV TRHDZ TRHDX PORT 0 A0-A7 FROM RI or DPL TAVWL TAVDV DATA IN A0-A7 FROM PCL INSTR IN PORT 2 P2[7:0] or A8-A15 FROM DPH A8-A15 FROM PCH 1259 F32.0 FIGURE 12-2: External Data Memory Read Cycle (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 50 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet TLHLL ALE TWHLH PSEN# TLLWL TWLWH WR# TAVLL TLLAX TQVWX TQVWH TWHQX PORT 0 A0-A7 FROM RI or DPL TAVWL DATA OUT A0-A7 FROM PCL INSTR IN PORT 2 P2[7:0] or A8-A15 FROM DPH A8-A15 FROM PCH 1259 F33.0 FIGURE TABLE 12-3: External Data Memory Write Cycle 12-8: External Clock Drive Oscillator 12MHz 33MHz Min 30.3 10.6 10.6 20 20 10 10 Max Min 0 0.35TCLCL 0.35TCLCL Variable Max 40 0.65TCLCL 0.65TCLCL Units MHz ns ns ns ns ns T12-8.2 1259 Symbol 1/TCLCL TCLCL TCHCX TCLCX TCLCH TCHCL Parameter Oscillator Frequency High Time Low Time Rise Time Fall Time Min 83 Max VDD - 0.5 0.7VDD 0.2 VDD - 0.1 TCLCX TCHCL TCLCL TCHCX TCLCH 1259 F34.0 0.45 V FIGURE 12-4: External Clock Drive Waveform (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 51 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet TABLE 12-9: Serial Port Timing Oscillator 12MHz Symbol TXLXL TQVXH TXHQX TXHDX TXHDV Parameter Serial Port Clock Cycle Time Output Data Setup to Clock Rising Edge Output Data Hold After Clock Rising Edge Input Data Hold After Clock Rising Edge Clock Rising Edge to Input Data Valid Min 1.0 700 50 11 0 700 0 170 Max 33MHz Min 0.364 170 Max Min 12TCLCL 10TCLCL - 133 2TCLCL - 117 2TCLCL - 50 0 10TCLCL - 133 Variable Max Units s ns ns ns ns ns T12-9.2 1259 INSTRUCTION ALE 0 1 2 3 4 5 6 7 8 TXLXL CLOCK TQVXH OUTPUT DATA WRITE TO SBUF INPUT DATA CLEAR RI TXHQX 0 1 TXHDV VALID VALID 2 TXHDX VALID 3 4 5 6 7 SET TI VALID VALID VALID VALID VALID SET R I 1259 F35.0 FIGURE 12-5: Shift Register Mode Timing Waveforms VIHT VHT VLT 1259 F36.0 VLOAD +0.1V VLOAD VLOAD -0.1V Timing Reference Points VOH -0.1V VOL +0.1V 1259 F37.0 VILT AC Inputs during testing are driven at VIHT (VDD -0.5V) for Logic "1" and VILT (0.45V) for a Logic "0". Measurement reference points for inputs and outputs are at VHT (0.2VDD + 0.9) and VLT (0.2VDD - 0.1) Note: VHT- VHIGH Test VLT- VLOW Test VIHT-VINPUT HIGH Test VILT- VINPUT LOW Test For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs, and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH = 20mA. FIGURE 12-6: AC Testing Input/Output Test Waveform FIGURE 12-7: Float Waveform (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 52 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet TO TESTER TO DUT CL 1259 F38.0 FIGURE 12-8: A Test Load Example VDD VDD VDD RST P0 EA# IDD VDD VDD = 2V VDD P0 RST EA# VDD IDD VDD CLOCK SIGNAL (NC) XTAL2 XTAL1 VSS 1259 F39.0 (NC) XTAL2 XTAL1 VSS 1259 F41.0 All other pins disconnected All other pins disconnected FIGURE 12-9: IDD Test Condition, Active Mode FIGURE 12-11: IDD Test Condition, Power-down Mode TABLE 12-10: Flash Memory Programming/ Verification Parameters1 Parameter2 VDD VDD VDD P0 RST EA# IDD Max 350 300 30 100 100 Units ms ms ms s s T12-10.0 1259 Chip-Erase Time Block-Erase Time Sector-Erase Time Byte-Program Time3 Re-map or Security bit Program Time CLOCK SIGNAL (NC) XTAL2 XTAL1 VSS 1259 F40.0 All other pins disconnected 1. For IAP operations, the program execution overhead must be added to the above timing parameters. 2. Program and Erase times will scale inversely proportional to programming clock frequency. 3. Each byte must be erased before programming. FIGURE 12-10: IDD Test Condition, Idle Mode (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 53 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet 13.0 PRODUCT ORDERING INFORMATION Device SST89x5xRC Speed XX Suffix1 X Suffix2 XX XX Environmental Attribute E1 = non-Pb Package Modifier I = 40 pins J = 44 leads Package Type N = PLCC P= PDIP Operation Temperature C = Commercial = 0C to +70C Operating Frequency 33 = 0-33MHz 25 = 0-25MHz Feature Set RC = Single Block, Dual Partitions Flash Memory Size 4 = C54 feature set + 16 KByte 2 = C52 feature set + 8 KByte Voltage Range E = 4.5-5.5V Product Series 89 = C51 Core 1. Environmental suffix "E" denotes non-Pb solder. SST non-Pb solder devices are "RoHS Compliant". (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 54 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet 13.1 Valid Combinations Valid combinations for SST89E52RC SST89E52RC-33-C-NJE SST89E52RC-33-C-PIE Valid combinations for SST89E54RC SST89E54RC-33-C-NJE SST89E54RC-33-C-PIE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 55 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet 14.0 PACKAGING DIAGRAMS 40 C L 1 Pin #1 Identifier .065 .075 2.020 2.070 12 4 places .600 .625 .530 .557 Base Plane Seating Plane .015 Min. .220 Max. .063 .090 .045 .055 .015 .022 .100 BSC .100 .200 .008 .012 .600 BSC 0 15 Note: 1. Complies with JEDEC publication 95 MS-011 AC dimensions (except as noted), although some dimensions may be more stringent. = JEDEC min is .115; SST min is less stringent 2. All linear dimensions are in inches (min/max). 40-pdip-PI-7 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. FIGURE 14-1: 40-pin Plastic Dual In-line Pins (PDIP) SST Package Code: PI TOP VIEW Optional Pin #1 Identifier .042 .048 .685 .695 .646 .656 1 44 SIDE VIEW .147 .158 .025 R. .045 BOTTOM VIEW .020 R. MAX. .042 x45 .056 .042 .048 .685 .695 .646 .656 .026 .032 .013 .021 .500 REF. .590 .630 .050 BSC. .020 Min. .026 .032 44-plcc-NJ-7 .050 BSC. .165 .180 .100 .112 Note: 1. Complies with JEDEC publication 95 MS-018 AC dimensions (except as noted), although some dimensions may be more stringent. = JEDEC min is .650; SST min is less stringent 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 4. Coplanarity: 4 mils. FIGURE 14-2: 44-lead Plastic Lead Chip Carrier (PLCC) SST Package Code: NJ S71259-04-000 1/07 (c)2007 Silicon Storage Technology, Inc. 56 FlashFlex MCU SST89E52RC / SST89E54RC Data Sheet TABLE Number 00 01 14-1: Revision History Description Date Feb 2005 Feb 2006 * * * * * * * * * * * * * * * * * * * * * Initial Release of Fact Sheet Added 40-PDIP devices and associated MPNs. Revised Function Block and Pin Assignment diagrams. Revised Valid Combinations product numbers. Removed 4KByte product from the fact sheet (SST89x51RC). Initial Release of Data Sheet Revised factory pre-programed BSL statements to pre-programming by user capabilities, pages 1 and 30. Changed 17/9/5 to 17/9 in first paragraph of Section 4.2 on page 27. Changed 2FFFH to 3FFFH in Figure 3-2 on page 11. Removed Industrial (-40C to +85C) from Temperature Range on page 1, and Operation Temperature on page 55. Changed TA = -40C to +85C to TA = -0C to +70C in Tables 12-6, 12-7, and 12-8 Removed 44-lead TQFP from Package Available page 1 and TQ = TQFP from Package Type on page 55. Removed "I" and "TQJE" packages from Valid Combinations on page 56. Removed Package diagram for TQFP, Figure 14-3 on page 58. Globally removed all 3V (SST89V52RC/SST89V54RC) references. Removed Pin Assignment for 44-lead TQFP on page 6. Edited Tables 4.-2, 4-3 (page 28), 9-1, (page 40), 11-2 (page 44), 12-1(page 45), 12-5 (page 46), and 12-7 (page 48) to remove 3V / 89V52EC references. Removed the entire "DC Characteristics for SST89V5xRC..." table. Removed SST89V52RC and SST89V54RC valid combinations page 55. Removed 44-lead Thin Quad Flat Pack (TQFP) package drawing. Edited figures 3-2 and 9-1 to remove 3V / 89V52EC. Changed reset value from 01x0x000b to 10000000b in Table 3-4, page 14. Changed reset value from 01x0x000b to 10000000b in SFCF register, page 16. Changed reset value from xxxxx0xxb to 1011111b in SFCF register, page 18. Changed external host mode: Read-back = 00H to 55H, page 38. Changed MOVD: Read-back = FFH to 00h, page 38. Changed document status from preliminary specification to data sheet. Changed FlashFlex51 to FlashFlex globally 02 Mar 2006 03 * * * * * * * May 2006 04 Jan 2007 Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.sst.com (c)2007 Silicon Storage Technology, Inc. S71259-04-000 1/07 57 |
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